1. Field of Use
The present invention relates to the testing of data processing systems and more particularly to the testing of cache systems.
2. Prior Art
It is well known in the art to provide cache units between a central processing unit (CPU) and a main store to improve overall system performance. However, since the cache unit is normally invisible to the operating system software during normal operation, errors or faults occurring within the cache unit are not detectable by such software. That is, when the cache is unable to provide correct data in response to a CPU request, the cache unit fetches the data from main store. This results in decreased system performance.
In view of the above, it becomes difficult to diagnose whether or not the cache unit is operating properly. In the past, elaborate software diagnostic routines were employed for testing cache operation which involved transferring information from main store to cache for comparison with such known information when read from cache. In order to eliminate the need for such elaborate software, one system arrangement enables the cache unit to be placed in a test and verification mode of operation wherein hardware faults can be signalled to the CPU. This arrangement is described in U.S. Pat. No. 4,190,885 issued Feb. 26, 1980 and is assigned to the same assignee as named herein.
While the above arrangement overcomes the prior art problems, it has been found that such test and verification operations are able to indirectly test certain portions of the cache unit. That is, while test and verification routines test or exercise various portions of the cache, the control of cache operations still resides with the cache unit. This can interfere with such testing making it difficult in certain instances to detect faults occurring within the cache memory portions.
In order to minimize the likeliness of the occurrence of faults within cache memory portions, factory and on-site test equipment and procedures are employed. Such procedures often employ in part the same diagnostic routines used by the CPU to test cache operation. An important difference is that in partitioned designs, cache unit can be disassembled to some extent during such testing thereby enabling independent testing of cache memory portions. Because of cost disadvantages, it becomes desirable to employ more integrated designs in which all the circuits of a cache unit are placed on a single board. Accordingly, it is no longer possible to independently test cache memory portions. Furthermore, it becomes more difficult to define interfaces between the different cache portions.
To overcome the above problems, one approach is to employ special interfaces and associated logic circuits for testing. Another approach is to use a "bed of nails" tester. The bed of nails tester probes the underside of a board to make available a larger number of points for observation and control. A disadvantage of this approach is that the tester must have enough test points to be able to control and observe each one of the nails or points. Further, the software for carrying out such tests is exceedingly complicated to generate and runs too slow to effectively test high speed memories.
Also, the mechanical fixtures required to hold the bed of nails are expensive to construct and difficult to align so that the normal forces on the probes are sufficient to guarantee reliable contacts. Also, when used for such testing, it becomes necessary to drive certain chip circuits to abnormal states in order to properly isolate different cache portions from each other for independent testing. However, it has been found that there is still some risk of incomplete testing of inter-connections and that substantial care must be taken to ensure that such circuits are not damaged from being overdriven.
Accordingly, it is a primary object of the present invention to provide testing apparatus which facilitates the detection of faults within the circuits of a cache unit constructed on a single board without causing damage to such circuits.
It is a further object of the present invention to provide testing apparatus which improves the detection of faults within the memory portions of a cache unit of single board construction.
It is still a further object of the present invention to provide apparatus for testing the circuits of a cache unit of single board construction prior to installation within a data processing system.